1. Field of the Invention
The present invention relates to a semiconductor storage and more particularly to a combination of a plurality of memory cell structures of an MOS static RAM.
2. Description of the Background Art
For a semiconductor storage comprising plural kinds of memory cells having different port structures and the like, conventionally, a semiconductor storage has been disclosed in Patent Document 1 (Japanese Patent Application Laid-Open No. 6-349275 (1994) gazette), for example. The semiconductor storage comprises a 3-port cell section which is 3-port simultaneous accessible and a 1-port cell section having one access port, and can be implemented by connecting them to at least a pair of bit lines in common.
On the other hand, it has been demanded that data to be accessed on a bit length unit are divided on a several-bit unit and individual data are accessed on the several-bit unit thus obtained by the division in a computer field or the like. Moreover, it has also been demanded that a part of bits are constituted to be accessible from a plurality of ports.
In the semiconductor storage of the Patent Document 1 described above, however, the 3-port cell section and the 1-port cell section share a bit line. For this reason, there is a problem in that both of the port cell sections cannot be accessed at the same time and the demand cannot be met.